Verilog File Format

Overview

Verilog is a hardware description language (HDL) used to model and design digital electronic systems at various levels of abstraction. Developed in the 1980s by Gateway Design Automation, Verilog enables engineers to describe hardware behavior, structure, and timing, making it essential for FPGA programming, ASIC design, and digital system verification.

Technical Details

• MIME Type: text/x-verilog
• File Extension: .v
• Category: Code
• First Appeared: 1984
• Standardized: IEEE 1364 (Verilog-95, Verilog-2001, Verilog-2005)
• Current Standard: SystemVerilog (IEEE 1800)

Structure and Syntax

Verilog uses a C-like syntax to describe hardware modules with ports, internal signals, and behavioral or structural descriptions.

Basic Module Structure

// Simple AND gate module
module and_gate (
    input wire a,
    input wire b,
    output wire y
);

    assign y = a & b;

endmodule

Module with Clock and Reset

module counter_8bit (
    input wire clk,
    input wire reset,
    input wire enable,
    output reg [7:0] count
);

    always @(posedge clk or posedge reset) begin
        if (reset)
            count <= 8'b0;
        else if (enable)
            count <= count + 1;
    end

endmodule

Hierarchical Design

// Full adder using half adders
module half_adder (
    input wire a,
    input wire b,
    output wire sum,
    output wire carry
);

    assign sum = a ^ b;
    assign carry = a & b;

endmodule

module full_adder (
    input wire a,
    input wire b,
    input wire cin,
    output wire sum,
    output wire cout
);

    wire s1, c1, c2;
    
    half_adder ha1 (.a(a), .b(b), .sum(s1), .carry(c1));
    half_adder ha2 (.a(s1), .b(cin), .sum(sum), .carry(c2));
    
    assign cout = c1 | c2;

endmodule

Data Types and Constants

Wire and Register Types

module data_types_example;

    // Wire types (continuous assignment)
    wire [7:0] data_bus;
    wire enable, clock, reset;
    wire [31:0] address;
    
    // Register types (procedural assignment)
    reg [7:0] counter;
    reg state, next_state;
    reg [15:0] memory [0:1023];  // Memory array
    
    // Integer and real types
    integer i, j;
    real frequency, delay_time;
    
    // Parameters and local parameters
    parameter WIDTH = 8;
    parameter DEPTH = 1024;
    localparam ADDR_WIDTH = $clog2(DEPTH);

endmodule

Constants and Literals

module constants_example;

    // Binary literals
    wire [7:0] bin_val = 8'b10110101;
    
    // Hexadecimal literals
    wire [15:0] hex_val = 16'hABCD;
    
    // Decimal literals
    wire [7:0] dec_val = 8'd255;
    
    // Octal literals
    wire [8:0] oct_val = 9'o377;
    
    // X (unknown) and Z (high impedance)
    wire [3:0] unknown = 4'bX01Z;

endmodule

Behavioral Modeling

Always Blocks

module behavioral_example (
    input wire clk,
    input wire reset,
    input wire [7:0] data_in,
    output reg [7:0] data_out,
    output reg valid
);

    // Sequential logic (clocked)
    always @(posedge clk or posedge reset) begin
        if (reset) begin
            data_out <= 8'b0;
            valid <= 1'b0;
        end else begin
            data_out <= data_in;
            valid <= 1'b1;
        end
    end
    
    // Combinational logic
    reg [7:0] processed_data;
    always @(*) begin
        case (data_in[7:6])
            2'b00: processed_data = data_in + 8'd1;
            2'b01: processed_data = data_in - 8'd1;
            2'b10: processed_data = data_in << 1;
            2'b11: processed_data = data_in >> 1;
            default: processed_data = data_in;
        endcase
    end

endmodule

State Machines

module traffic_light_fsm (
    input wire clk,
    input wire reset,
    input wire sensor,
    output reg [2:0] lights  // [red, yellow, green]
);

    // State encoding
    parameter IDLE = 2'b00,
              GREEN = 2'b01,
              YELLOW = 2'b10,
              RED = 2'b11;
    
    reg [1:0] current_state, next_state;
    reg [7:0] timer;
    
    // State register
    always @(posedge clk or posedge reset) begin
        if (reset) begin
            current_state <= IDLE;
            timer <= 8'b0;
        end else begin
            current_state <= next_state;
            if (current_state != next_state)
                timer <= 8'b0;
            else
                timer <= timer + 1;
        end
    end
    
    // Next state logic
    always @(*) begin
        case (current_state)
            IDLE: next_state = sensor ? GREEN : IDLE;
            GREEN: next_state = (timer >= 50) ? YELLOW : GREEN;
            YELLOW: next_state = (timer >= 10) ? RED : YELLOW;
            RED: next_state = (timer >= 30) ? GREEN : RED;
            default: next_state = IDLE;
        endcase
    end
    
    // Output logic
    always @(*) begin
        case (current_state)
            IDLE:   lights = 3'b100;  // Red only
            GREEN:  lights = 3'b001;  // Green only
            YELLOW: lights = 3'b010;  // Yellow only
            RED:    lights = 3'b100;  // Red only
            default: lights = 3'b000;
        endcase
    end

endmodule

Structural Modeling

Gate-Level Description

module logic_circuit (
    input wire a, b, c, d,
    output wire y
);

    wire n1, n2, n3;
    
    // Gate instantiations
    and gate1 (n1, a, b);
    or  gate2 (n2, c, d);
    xor gate3 (n3, n1, n2);
    not gate4 (y, n3);

endmodule

Module Instantiation

module processor_top (
    input wire clk,
    input wire reset,
    input wire [31:0] instruction,
    output wire [31:0] data_out
);

    wire [31:0] alu_result, reg_data1, reg_data2;
    wire [4:0] reg_addr1, reg_addr2, reg_dest;
    wire reg_write_enable;
    
    // ALU instantiation
    alu_32bit alu_inst (
        .a(reg_data1),
        .b(reg_data2),
        .operation(instruction[31:26]),
        .result(alu_result),
        .zero_flag(),
        .overflow_flag()
    );
    
    // Register file instantiation
    register_file reg_file (
        .clk(clk),
        .reset(reset),
        .read_addr1(reg_addr1),
        .read_addr2(reg_addr2),
        .write_addr(reg_dest),
        .write_data(alu_result),
        .write_enable(reg_write_enable),
        .read_data1(reg_data1),
        .read_data2(reg_data2)
    );

endmodule

Advanced Features

Generate Statements

module parameterized_adder #(
    parameter WIDTH = 8
) (
    input wire [WIDTH-1:0] a,
    input wire [WIDTH-1:0] b,
    input wire cin,
    output wire [WIDTH-1:0] sum,
    output wire cout
);

    wire [WIDTH:0] carry;
    assign carry[0] = cin;
    
    genvar i;
    generate
        for (i = 0; i < WIDTH; i = i + 1) begin : full_adder_gen
            full_adder fa (
                .a(a[i]),
                .b(b[i]),
                .cin(carry[i]),
                .sum(sum[i]),
                .cout(carry[i+1])
            );
        end
    endgenerate
    
    assign cout = carry[WIDTH];

endmodule

Memory Modeling

module ram_dual_port #(
    parameter ADDR_WIDTH = 8,
    parameter DATA_WIDTH = 32,
    parameter DEPTH = 256
) (
    input wire clk,
    
    // Port A
    input wire [ADDR_WIDTH-1:0] addr_a,
    input wire [DATA_WIDTH-1:0] data_in_a,
    input wire we_a,
    output reg [DATA_WIDTH-1:0] data_out_a,
    
    // Port B
    input wire [ADDR_WIDTH-1:0] addr_b,
    input wire [DATA_WIDTH-1:0] data_in_b,
    input wire we_b,
    output reg [DATA_WIDTH-1:0] data_out_b
);

    reg [DATA_WIDTH-1:0] memory [0:DEPTH-1];
    
    // Port A
    always @(posedge clk) begin
        if (we_a)
            memory[addr_a] <= data_in_a;
        data_out_a <= memory[addr_a];
    end
    
    // Port B
    always @(posedge clk) begin
        if (we_b)
            memory[addr_b] <= data_in_b;
        data_out_b <= memory[addr_b];
    end

endmodule

Testbenches and Verification

Basic Testbench

module counter_testbench;

    reg clk, reset, enable;
    wire [7:0] count;
    
    // Device under test
    counter_8bit dut (
        .clk(clk),
        .reset(reset),
        .enable(enable),
        .count(count)
    );
    
    // Clock generation
    initial clk = 0;
    always #5 clk = ~clk;  // 10 time unit period
    
    // Test sequence
    initial begin
        // Initialize
        reset = 1;
        enable = 0;
        
        // Release reset
        #20 reset = 0;
        
        // Enable counting
        #10 enable = 1;
        
        // Run for several clock cycles
        #200;
        
        // Disable counter
        enable = 0;
        #50;
        
        // Test reset during operation
        enable = 1;
        #100 reset = 1;
        #20 reset = 0;
        
        #100 $finish;
    end
    
    // Monitor outputs
    initial begin
        $monitor("Time=%0t reset=%b enable=%b count=%d", 
                 $time, reset, enable, count);
    end

endmodule

Advanced Testbench with Tasks

module advanced_testbench;

    reg clk, reset;
    reg [7:0] data_in;
    reg write_enable;
    wire [7:0] data_out;
    
    memory_module dut (
        .clk(clk),
        .reset(reset),
        .data_in(data_in),
        .write_enable(write_enable),
        .data_out(data_out)
    );
    
    // Clock generation
    initial clk = 0;
    always #5 clk = ~clk;
    
    // Test tasks
    task write_memory(input [7:0] data);
        begin
            @(posedge clk);
            data_in = data;
            write_enable = 1;
            @(posedge clk);
            write_enable = 0;
        end
    endtask
    
    task reset_system;
        begin
            reset = 1;
            #20 reset = 0;
        end
    endtask
    
    // Test sequence
    initial begin
        reset_system();
        
        write_memory(8'hAA);
        write_memory(8'h55);
        write_memory(8'hFF);
        
        #100 $finish;
    end

endmodule

Development Tools

Simulation Tools

• ModelSim: Industry-standard Verilog simulator
• VCS: Synopsys VCS simulator
• Icarus Verilog: Open-source Verilog simulator
• Verilator: Fast Verilog simulator and linter
• XSIM: Xilinx simulation environment

Synthesis Tools

• Quartus Prime: Intel/Altera FPGA development
• Vivado: Xilinx FPGA development suite
• Design Compiler: Synopsys ASIC synthesis
• Yosys: Open-source synthesis framework

IDE and Editors

• Eclipse with HDT: Hardware development tools
• Visual Studio Code: Verilog extensions available
• Emacs/Vim: Syntax highlighting support
• Sigasi Studio: Professional HDL IDE

Common Use Cases

FPGA Development

• Digital signal processing implementations
• Custom processor designs
• Communication protocol implementations
• Real-time control systems

ASIC Design

• Microprocessor components
• Memory controllers
• Interface circuits
• System-on-chip (SoC) designs

Verification and Testing

• Functional verification of digital designs
• Coverage-driven verification
• Assertion-based verification
• Hardware-software co-verification

Best Practices

Coding Style

• Use meaningful signal and module names
• Follow consistent naming conventions
• Add comments for complex logic
• Use parameters for configurable designs
• Separate combinational and sequential logic

Design Guidelines

• Avoid latches (use proper if-else structures)
• Use non-blocking assignments for sequential logic
• Use blocking assignments for combinational logic
• Initialize all registers properly
• Consider reset strategies (synchronous vs asynchronous)

Verification Strategy

• Write comprehensive testbenches
• Use assertions for property checking
• Implement coverage metrics
• Test corner cases and error conditions
• Use formal verification for critical paths

Verilog remains essential for digital design, providing the foundation for modern FPGA and ASIC development across industries from telecommunications to automotive electronics.